Processing logic modeling and execution

ABSTRACT

Provides processing logic modeling and executing methods, systems and apparatus. These facilitate collaboration between business analyst and IT staff for process modeling and maintenance of the consistency between business level design and IT implementation design. A task is decomposed into sub-tasks and is represented by a tree. Annotations to the nodes of the tree are used to represent the relations between the sub-tasks. A processing logic is thus completed. When executing the processing logic, traversing the tree follows according to the annotations.

TECHNICAL FIELD

The present application generally relates to processing logic modelingand execution, especially to a processing logic modeling method, aprocessing logic executing method, a processing logic modeling apparatusand a processing logic executing apparatus.

BACKGROUND OF THE INVENTION

Processing logic represents the procedural steps to accomplish a processor a complex task. Processing logic modeling is a common requirementwhen describing a process in a structured way or in order to implementit on IT system. To improve the business process's visibility andflexibility for change, business and industries have striven to captureand streamline the business processes.

Well known workflow system has been widely used in this field. Normallyit features a directed graph based flow method to describe a structuredset of activities designed to produce a specific output. However, suchflow model is not easy to understand if the process is complex,especially for business analyst. This brings big gap for process designbetween business operation level and IT implementation level.

A complex process is not easy to be decomposed to simple atomicprocesses due to the complicated relationship between entities of a flowmodel. So there is no clear composition view of key tasks of a process.Prior art includes a software product well known as WBS Chartpro havinga URL (purposely broken into segments),

-   -   http://    -   followed by:    -   www.    -   followed by:    -   criticaltools.com.

WBS Chartpro is a project plan tooling, which could help to plan anddisplay projects' schedule using a tree-style diagram known as a WorkBreakdown Structure (WBS) Chart. WBS charts display the structure of aproject showing how the project is broken down into summary and detaillevels. Plan new projects using an intuitive “top-down” approach ordisplay existing Microsoft Project plans in an easy to understanddiagram. Although this application takes use of tree-style diagram todescribe a detailed project plan, it is not process descriptioninitiative, so it has no capability to streamline the procedure of aprocess.

As another example, WO 99/60372 (Apparatus and Method for Monitoring andControlling Laboratory Information and/or Instruments) disclosed asystem for facilitating the handling of laboratory information. Usercould select predetermined task, drag and drop in the tooling interfaceto build a task sequence in a tree structure, and when running theprocessor executes the sequence of tasks in turn by reference to thestatic and dynamic laboratory data. This invention is a domain specificapplication. Although it also features a tree-style structure todescribe a processing logic, it targets to describe sequence processingin the specific domain but has no enough and necessary processing logicmodeling capabilities, such as parallel processing, loop and sub-logicsupport.

Again an example. U.S. Pat. No. 6,092,048 (Task Execution SupportSystem) disclosed a task execution support system which supports theuser to execute a task in accordance with the progress of task processlisted-up as network type flow. A task management server includes amemory unit for memorizing task information, an action entry comprisinga task, an event rule and a main task and sub-task structure, and eachof a plurality of client machines includes a task informationdisplay/operation unit which enables each user to operate informationduring a task is executed. In the modeling method in this invention, thesub-tasks structure could only be sequential, no parallel, and it'sprocessing logic modeling tool is more like a task registrationinterface and has no extensive editing function.

SUMMARY OF THE INVENTION

To solve these problems, an aspect of the invention is to provideprocessing logic modeling and executing methods and apparatus, tofacilitate collaboration between business analyst and IT staff forprocess modeling and maintenance of the consistency between businesslevel design and IT implementation design.

An aspect of the invention provides a processing logic modeling methodfor modeling a task. An example of the method includes: a decomposingstep for decomposing said task into at least one level of sub-tasks; atree structure forming step for forming a tree structure from said taskand various levels of sub-tasks resulted from decomposing the task; anannotating step for, according to the relations between the sub-tasks,annotating the nodes of the tree, thus obtaining a processing logicmodel for performing said task.

Correspondingly, the invention provides a method for executing theprocessing logic, established according to the method given above,comprising: traversing the tree according to the annotations, andperforming the leaf nodes of the tree according to the annotations, thuscompleting the execution of the task.

An aspect of the invention further provides a processing logic modelingapparatus that may apply the above method, for modeling a task,comprising an editor and an interpreter, for mapping the tree and theannotations into script of the processing logic, the editor comprising:a tree editor for editing a tree corresponding to a processing logic andshowing how the task is decomposed into at least one level of sub-tasks,and annotation editor for editing annotations for the nodes of the tree,the annotations representing the relations between the nodes of variouslevels.

BRIEF DESCRIPTION OF THE DRAWINGS

Other aspects, features and advantages of the invention will become moreapparent after reading the following detailed description ofadvantageous embodiments. The accompanying drawings, which areincorporated in and constitute a part of the specification, illustrateembodiments of the invention and, together with the description, serveto explain the principles of the invention. In the drawings:

FIG. 1 is a schematic view of a logic tree established according to theinvention;

FIG. 2 is a processing logic script corresponding to the tree as shownin FIG. 1;

FIG. 3 is a first example showing sub-tasks decomposing according to theinvention;

FIG. 4 is a schematic view showing establishing a tree structure andannotating the tree based on the sub-tasks shown in FIG. 3;

FIG. 5 is a second example showing sub-tasks decomposing according tothe invention;

FIG. 6 is a schematic view showing establishing a tree structure andannotating the tree based on the sub-tasks shown in FIG. 5;

FIG. 7 is a block view showing a processing logic modeling apparatus ofthe invention;

FIG. 8 is an exemplary visual interface of the processing logic modelingapparatus as shown in FIG. 7; and

FIG. 9 is a schematic view showing a system employing the processinglogic modeling apparatus and the processing logic executing apparatus ofthe invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention provides processing logic modeling and executingmethods, systems and apparatus, to facilitate collaboration betweenbusiness analyst and IT staff for process modeling. while maintainingthe consistency between business level design and IT implementationdesign. To this end, the invention adopts a strategy ofdivide-and-conquer to decompose a task into sub-tasks and express it inform of a tree, use annotations to the nodes of the tree to representthe relations between the sub-tasks, and thus complete a processinglogic. When executing the processing logic, the tree is traversedaccording to the annotations. The traversing includes depth-firsttraversing and broadness-first traversing. The executing apparatusautomatically select the depth-first traversing algorithm or thebroadness-first traversing algorithm according to the annotations to thenodes, and thus execute the predetermined processing logic.

Specifically, the invention provides a processing logic modeling methodfor modeling a task, comprising: a decomposing step for decomposing saidtask into at least one level of sub-tasks; a tree structure forming stepfor forming a tree structure from said task and various levels ofsub-tasks resulted from decomposing the task; an annotating step for,according to the relations between the sub-tasks, annotating the nodesof the tree, thus obtaining a processing logic model for performing saidtask.

In the invention, the leaf nodes of the tree can include only one actionor sub-logic node, wherein, the action node corresponds to atomic actionprogram that could be invoked, and the sub-logic node corresponds tosub-logic that could be invoked. The action nodes and the sub-logicnodes may only define normative interface description. Only when to beexecuted, will the implementation modules (applications, services,parts, and etc.) of the action or the sub-logic be bound to the actionor sub-logic nodes, as long as the action or the sub-logic could provideinterface specification complying with that defined by the nodes.Consequently, it is sufficient for the logic designing staff to definethe functions and the interfaces of the action nodes or the sub-logicnodes, and the action or the sub-logic may be implemented in variousways. Therefore, the design and implementation of logic will be moreflexible. That is, such capability of “delayed binding” enables thelogic designing staff to have more freedom to select or change theimplementation modules of the actions or sub-logics.

The annotations may comprising at least one of the following:precondition defining the condition to be met for performing thecorresponding node; postcondition defining the condition to be met forleaving the corresponding node; pre-task defining the task to beperformed before performing the corresponding node; post-task definingthe task to be performed before leaving the corresponding node; and thetype of intermediate node, stipulating whether the children of theintermediate node should be performed sequentially or in parallel.

Correspondingly, the invention provides a method for executing theprocessing logic established according to above method, comprising:traversing the tree according to the annotations, and performing theleaf nodes of the tree according to the annotations, thus completing theexecution of the task.

The invention further provides a processing logic modeling apparatusthat may apply the above method, for modeling a task, comprising aneditor and an interpreter, for mapping the tree and the annotations intoscript of the processing logic, the editor comprising: a tree editor forediting a tree corresponding to a processing logic and showing how thetask is decomposed into at least one level of sub-tasks, and annotationeditor for editing annotations for the nodes of the tree, theannotations representing the relations between the nodes of variouslevels.

In the apparatus, the tree editor and the annotation editor mayrepresent the tree and the annotations with graphics. Correspondingly,the interpreter may comprises means for mapping a predeterminedgraphical element into a predetermined script section. The apparatus mayfurther comprises a debugger for simulatively performing the processinglogic, either automatically or manually, either globally or locally, soas to find out and display the potential bug in the resulted processinglogic.

Corresponding to the above-mentioned processing logic modelingapparatus, the invention provides a processing logic executingapparatus, characterized in comprising a identifying means, which iscapable of identifying the processing logic represented by the treeestablished by the above-mentioned processing logic modeling apparatusand the nodes of the tree, so that the executing apparatus traverses thetree according to the logic script and executes the processing logic.

Advantageous embodiments of the present invention will now be describedwith reference to the accompanied drawings. Note that throughout thespecification including the drawings, identical or corresponding partsare denoted with like reference signs. Divide-and-conquer is one of themost widely used strategies for problem solving, that is, a task wouldoften be divided into sub-tasks. If any of the sub-tasks is too complexto address, further sub-division is done until all of them are ready tobe attacked. Divide-and-conquer strategy gives a nice sub-tasks treestructure to define a complex task to be solved. However, as discussedin the background of the invention, a conventional tree has no completecapability for logic modeling. In the present invention, annotations tothe nodes of a tree are used to express the transition relations betweenthe sub-tasks contained in a complex task.

FIG. 1 is a schematic view of an exemplary logic tree used in thepresent invention. As illustrated in FIG. 1, there are 3 node types in aprocessing: root node, intermediate node and leaf node. In the presentinvention, the leaf node may be action node or sub-logic node. Thesenodes have corresponding elements which could be used to model complexlogic and define execution rules. Root node is the root element, itcontains global information of the processing logic to be designed, suchas logic ID, version, parameters, and it could only has one child, thischild must be an intermediate node, such as InterNode1 shown in thedrawing.

An intermediate node can has one or more children. The children can beintermediate node, action node or sub-logic node. According to theinvention, annotation may be attached to the intermediate nodes. Forexample, annotation may be used to define the type of an intermediatenode, and thus determine the behaviour of its children: to be executedin sequence or in parallel. For example, as shown in FIG. 1, the smallsquares below the intermediate nodes represent the types of theintermediate nodes: the Annotation 1 represented by the black squaresshows that the children of the corresponding intermediate node should beexecuted sequentially, and the Annotation 2 represented by the blanksquares shows that the children of the corresponding intermediate nodeshould be executed in parallel. Apparently, any other graphic elementsmay be used to represent said annotations. During execution, the type ofthe intermediate node will automatically determine to adopt adepth-first traverse algorithm or a broadness-first traverse algorithm.If the attribute of an intermediate node is “sequentially executing”,then its children are traversed with a depth-first traverse algorithm;or if the attribute of an intermediate node is “executing in parallel”,then its children are traversed with a broadness-first traversealgorithm. Furthermore, variable can be defined in an intermediate node,and these variables can be used by the intermediate node and it'schildren.

Sub-logic node calls another processing logic. It will prepare thearguments for the sub-logic invocation. In processing logic, variableparameters are used, so the input arguments must be defined by variablenames. The variable should be defined in any of its parent node(intermediate node). In sub-logic, these variables may be changed, andit will reflect to the parent logic's context. So sub-logic node has noreturn values, it uses variable parameters to pass value changes back tothe parent logic.

Action node calls existing action program to execute an action. Actionnode will prepare the arguments for the action and get the return valuefrom the action. Here the arguments must use variable name to presentthe arguments' value. As action node has return values, it does not usevariable parameters, but value parameters. Action node could have morethan one return values, which can be filled back into the variable spaceof the logic context respectively.

In addition to the afore-discussed annotations relating to the types ofthe intermediate nodes, intermediate node, action node and sub-logicnode may be annotated according to the relations between correspondingsub-tasks. The annotations may have 4 elements: precondition,postcondition, pre-task and post-task, to control the execution of thenodes.

Precondition defines the entry condition of the node. If preconditionreturns false, the node will not be executed. For example, as shown inFIG. 6, a precondition may be used to control the execution of theaction nodes Action 2, Action 3 and Action 4. For example, assuming thatAction 2 will be executed when an integer a equals to 1, Action 3 willbe executed when said integer a equals to 2 and Action 4 will beexecuted when said integer a is neither 1 nor 2, then for each of Action2, Action 3 and Action 4, a precondition may be set (not shown in thefigure): the precondition of Action 2 is “a=1”, the precondition ofAction 3 is “a=2” and the precondition of Action 4 is “a< >1 and a< >2.Thus, when the branch tree of the intermediate node InterNode2 istraversed, if a=1, then the precondition of Action 2 is true and Action2 will be executed, and the preconditions of Action 3 and Action 4 arefalse and Action 3 and Action 4 will not be executed.

Postcondtion is used for checking execution state. It can be used to,for example, implement loop process. For example, assuming that avariable b has an initial value “0” and will be incremented every time anode is executed. By saying “a node is executed”, it means, if the nodeis a leaf node, then the leaf node is executed; if the node is anintermediate node, then the branch tree of the intermediate node isexecuted. If the postcondition of the node is set as “b>=50”, then, whenb is smaller than 50, the node (or corresponding branch tree) will beexecuted; otherwise the postcondition is met and the execution of thenode (or corresponding branch tree) is terminated. As a result, the node(or its branch tree) is repeatedly executed 50 times.

Pre-tasks are executed when entering a node. In general pre-task mayprepare context and initial variables for the operations of the node.Specifically, Pre-task may prepare data form for the corresponding node,or initialize the variables (that is, assign values to the variables).

Post-tasks are executed when leaving a node. The post-tasks may includesetting return value, clearing error state and etc. As a specificexample, the post-tasks may write the result of the execution of thecorresponding nodes into databases, or record the execution status ofthe corresponding nodes into the system log.

FIG. 2 shows a processing logic script corresponding to the logic treeshown in FIG. 1. The script is written in XML (extensible markinglanguage). Any person skilled in the art knows that the processing logicmay be written in any available language.

With the tree having the above features, it is possible to model most ofthe processing logic. According to the experiments of the inventors, theinvented processing logic has the capability to model most of theEindHoven workflow patterns.

Here we use two simple examples to explain the processing logic modelingmethod and the processing logic modeling apparatus according to theinvention. First the task to be solved is analyzed and decomposed intosub-tasks. As illustrated in FIG. 3, if, as a result of the analyzingand decomposing, a task should be fulfilled by performing two actions insequence, then, according to the invention, the task could be presentedas a processing logic tree as shown in FIG. 4. The intermediate noderepresents the problem to be solved, which could be divided into twosequential sub-tasks, Action 1 and Action 2. According to the invention,to model the processing logic, the nodes of the tree are to be annotatedappropriately. In the present example, Action 1 and Action 2 are to beexecuted sequentially. Therefore, their parent node, that is saidintermediate node, is attached Annotation 1 stipulating that thechildren shall be executed sequentially.

When executing the processing logic, said tree is traversed. Thetraversing first reaches the intermediate node. Based on the type of theintermediate node represented by the Annotation 1, it is determined thatthe intermediate node's children shall be executed sequentially.Consequently, with respect to the children, that is, leaf nodes Action 1and Action 2, a depth-first traversing algorithm is performed tocomplete said task.

A person skilled in the art knows that it is not important what is thevisual appearance of the tree shown in FIG. 4, and the tree is a logictree in nature. In fact, the tree may be in any form, such as in theform of a logic script as shown in FIG. 2, or in the form of the outlineas shown in FIG. 8, which will be described below.

Another example will be discussed below. As illustrated in FIG. 5,through analyzing, it is known that to fulfill a task, Action1 should beperformed first, and then according to the condition evaluation result,Action2 or Action3 or Action4 would then be performed.

The task could be presented as a processing logic tree in FIG. 6. In thedrawing, the intermediate node InterNode 1 represents the problem to besolved, which could be divided into two sequential sub-tasks, Action1and InterNode 2. The InterNode 2 has three parallel sub-tasks, Action2,Action3, and Action4. Each of these three sub-tasks has a preconditiondefinition as discussed above, and if the precondition is satisfied,then the corresponding action would then be performed.

According to the invention, to model the processing logic, the nodes ofthe tree are to be annotated appropriately. In the present example,Action 1 and InterNode 2 are to be executed sequentially. Therefore,their parent node, that is InterNode 1, is attached Annotation 1stipulating that the children shall be executed sequentially. Similarly,the InterNode 2 is attached Annotation 2 stipulating that its childrenshall be executed in parallel. The rest of the action nodes are attachedprecondition annotations for checking whether the above-mentioned threeconditions are met, respectively.

When executing the processing logic, the tree is traversed. Thetraversing first reaches the intermediate node InterNode 1. Based on thetype of the intermediate node represented by the annotation, it isdetermined that the intermediate node's children shall be executedsequentially. Consequently, with respect to the children, that is, leafnode Action 1 and intermediate node InterNode 2, a depth-firsttraversing algorithm is performed. Based on the type of the intermediatenode InterNode 2 represented by the annotation, it is determined thatthe intermediate node's children shall be executed in parallel.Consequently, with respect to the children, that is, leaf nodes Action2, Action 3 and Action 4, a broadness-first traversing algorithm isperformed. When executing the three leaf nodes, first checking theirpreconditions, and only when their preconditions are met, respectively,will the respective action nodes be executed. Thus the task iscompleted.

Above discussed are only two simple examples for illustrating theprinciple of the invention. In fact, any annotation may be attached toany node to achieve a particular object. For example, by settingpostconditions for any desired leaf nodes or intermediate nodes, therecursion execution of the corresponding leaf node or branch tree couldbe realized for fulfilling a loop process requirement. And communicationmechanism for leaf node's interaction could be designated in theannotations, and so on. All of these make the invented method capable ofdescribing a complex graph type flow.

Corresponding to the method of the invention, the invention furtherprovides a processing logic modeling apparatus, which could beimplemented in a computer or any other form of computing device.

As shown in FIG. 7, a processing logic modeling apparatus 700essentially comprises an editor 702 and an interpreter 804, both ofwhich may be realized in the microprocessor such CPU and the like andmemory device of a computing device. The editor further comprises inputdevice(s) 710 and output device(s) 712. The editor includes a treeeditor 706 and an annotation editor 708, through which, and through theinput device(s) such as a mouse and a keyboard and the output device(s)such as a display, a tree and annotations to the nodes of the tree maybe edited according to the method as discussed above. The interpreter704 functions to map the tree and the annotations to the nodes thereofinto processing logic script.

As discussed above, the tree and the annotations may be manifested inany form. The most convenient form is graphic form. Specifically, theannotations may be formatted text, or graphics with text, and the like.Obviously, a person skilled in the art will appreciate that the tree andthe annotations may be in any form. Here, assuming various graphicelements are used to express the nodes and their annotations, that is,their attributes. Then, the editor may further comprise a graphical userinterface displayed in said output device. In the interface, variousgraphical elements, such as elements relating to the tree structure andelements relating to the annotations (such as, as discussed above, theblank and black squares, graphical elements representing theprecondition “a=1” and having the text “a=1” or the like, and etc.), maybe provided in advance or may be defined by the user. Each graphicalelement corresponds to a particular segment of the processing logicscript. Then, every time a new graphical element is added into the tree,for example, by dragging a particular graphical element in a graphicalelement library and dropping it to a proper position in the tree with amouse, the interpreter will add a corresponding script segment into theprocessing logic script. For, example, the graphical elementrepresenting a precondition may be positioned above the graphicalelement of the corresponding node, and the graphical elementrepresenting a postcondition may be positioned below the graphicalelement of the corresponding node. As a result, as the tree and theannotations are edited, the processing logic script is generateddynamically.

A person skilled in the art may conduct the graphical editing with anygraphical editing means. The operation of mapping the graphical elementsto the script segments also belongs to conventional technical means.

FIG. 8 shows an exemplary user interface 800 of the processing logicmodeling apparatus of the invention. The window contains 4 parts,Navigator 802, Editor 804, Outline 806 and Property Page 808. The datamodel of the designed logic would be synchronized among these fourdifferent windows.

A set of graphic editing facilities are provided in the Editor and maybe embodied in the main menu and the tool bars, and allow the user tovisually design the processing logic by drawing a tree structure toillustrate how a relatively complex task is decomposed into sub-tasks. Anode of the tree represents a sub-task, which can also be divided intoseveral smaller sub-tasks, while the leaves are the final “atomic”actions. Properties on the tree, such as the data, transition rule,corresponding action programs, can be associated with each node andleaf. The various graphical elements as discussed above may be providedin the form of menu or tool bars in the prior art editor, and may bedefined by the user. The interpreter as discussed above (not manifestedin the graphic user interface) can dynamically map the logic graph intoprocessing logic script such as in XML format. To facilitate actionreference, is also provided an interface to retrieve action programregistration information from an action library.

To serve the objective for business executive review, the Editorprovides strong capability of making comments. User could make commentson every node, and also could make general comments as sticky note onthe drawing. Property page could be used to set the respectiveproperties' value for every node. Error alert, simulation debugging,deployment related features may also be provided to facilitate thedevelopment, debugging and deployment of the processing logic.

To run the processing logic established by the processing logic modelingmethod and apparatus of the invention, the conventional processing logicexecuting engine needs to be modified correspondingly. That is, meansfor identifying and interpreting the annotations as discussed above isnecessary. As discussed above, in the processing logic script, saidannotations are manifested as code sections in particular format. Thus,the processing logic executing apparatus (engine) traverses the treeaccording to the structure and the annotations thereof, thus completesthe execution of the processing logic.

The environment for processing logic modeling (Design time support) andthe environment for processing logic executing (Run time support) areconsistent with the prior art except those disclosed in the presentdisclosure. Therefore, further detailed description thereof is omitted.The following is only a summary, with reference FIG. 9, of the systemsupporting designing and executing processing logic (Design time support902 and Run time support 904) and its operation.

As shown in FIG. 9, the user may design a new processing logic with theprocessing logic modeling apparatus 700 of the invention. The processinglogic may be deployed to the logic library after it is confirmed to beusable through its simulation run on the staging server 906.

In the run time support 904, a processing logic could be invoked byreceiving a request message through the execution engine invocationinterface. The message dispatcher would pickup the message in theinbound queue, and bind the message to the corresponding processinglogic, the logic script would then be loaded from the logic library 908into the executing apparatus (engine) 910 kernel. And then the executingapparatus instantiates a processing logic instance by feeding the datacontained in the business message. The logic would be executed on theexecuting apparatus by traversing the logic tree. Action invocationbroker (AIB) 912 enables the executing apparatus 910 to invoke actionsdefined in the logic. AIB would retrieve action corresponding toinvocation parameters from the action library 914 and then perform theinvocation. When the tree contains sub-logic nodes, the executingapparatus may invoke sub-logics from the logic library. The executingapparatus may further provide Runtime Administration Console formonitoring the runtime status of the executing apparatus and managingthe logic library.

From above description, it could be seen that the invention has thefollowing advantages:

-   -   The annotated tree could meet most of the requirements of        processing logic modeling. The invented modeling method is very        easy to learn. It provides a clear tree structure view on the        objectives of a process and its detailed tasks, which make it        easy to understand by both business executives and IT staffs.    -   The hierarchical tree-style processing logic structure could        facilitate the collaboration between business analyst and IT        staff for process modeling. Only the leaf node on the tree will        be attached with real action code. Business analyst could design        the task breakdown structure first, IT staff would then work out        the detailed data definition for every node. So it could help to        bridge the gap between the business analyst and the IT staff,        and maintain the consistency between business level design and        IT implementation design.    -   Each branch of the processing logic tree is an atomic        description on a set of tasks or procedures. So it is very easy        to be componentized as a sub-logic, which could improve the        atomic processing logic's reuseability and make the main logic        is clear and easy to understand.    -   Taking use of the design tooling of the invention, to design a        processing logic, no programming or script coding is required.        Rather, drag and drop functions of each object in the tooling        environment to define a process. Flexible graphic editing        facilities are also provided. The logic XML script could be        dynamically generated upon the graphic editing.

While the invention has been described with reference to specificembodiments disclosed herein, it is not confined to the details setforth herein, and this application is intended to cover all thevariations or equivalents that are obvious to a person skilled in theart having read the specification. The present invention can be realizedin hardware, software, or a combination of hardware and software. Avisualization tool according to the present invention can be realized ina centralized fashion in one computer system, or in a distributedfashion where different elements are spread across severalinterconnected computer systems. Any kind of computer system—or otherapparatus adapted for carrying out the methods and/or functionsdescribed herein—is suitable. A typical combination of hardware andsoftware could be a general purpose computer system with a computerprogram that, when being loaded and executed, controls the computersystem such that it carries out the methods described herein. Thepresent invention can also be embedded in a computer program product,which comprises all the features enabling the implementation of themethods described herein, and which—when loaded in a computer system—isable to carry out these methods.

Computer program means or computer program in the present contextinclude any expression, in any language, code or notation, of a set ofinstructions intended to cause a system having an information processingcapability to perform a particular function either directly or afterconversion to another language, code or notation, and/or reproduction ina different material form.

Thus the invention includes an article of manufacture which comprises acomputer usable medium having computer readable program code meansembodied therein for causing a function described above. The computerreadable program code means in the article of manufacture comprisescomputer readable program code means for causing a computer to effectthe steps of a method of this invention. Similarly, the presentinvention may be implemented as a computer program product comprising acomputer usable medium having computer readable program code meansembodied therein for causing a function described above. The computerreadable program code means in the computer program product comprisingcomputer readable program code means for causing a computer to effectone or more functions of this invention. Furthermore, the presentinvention may be implemented as a program storage device readable bymachine, tangibly embodying a program of instructions executable by themachine to perform method steps for causing one or more functions ofthis invention.

It is noted that the foregoing has outlined some of the more pertinentobjects and embodiments of the present invention. This invention may beused for many applications. Thus, although the description is made forparticular arrangements and methods, the intent and concept of theinvention is suitable and applicable to other arrangements andapplications. It will be clear to those skilled in the art thatmodifications to the disclosed embodiments can be effected withoutdeparting from the spirit and scope of the invention. The describedembodiments ought to be construed to be merely illustrative of some ofthe more prominent features and applications of the invention. Otherbeneficial results can be realized by applying the disclosed inventionin a different manner or modifying the invention in ways known to thosefamiliar with the art.

1. A processing logic modeling method for modeling a task, comprising: adecomposing step for decomposing said task into at least one level ofsub-tasks; a tree structure forming step for forming a tree structurefrom said task and various levels of sub-tasks resulted from decomposingthe task; and an annotating step for, according to the relations betweenthe sub-tasks, annotating the nodes of the tree, thus obtaining aprocessing logic model for performing said task.
 2. The method accordingto claim 1, wherein said tree structure forming step comprises: formingleaf nodes comprising at least one of action node and sub-logic node,wherein, the action node corresponds to atomic action program that couldbe invoked, and the sub-logic node corresponds to sub-logic that couldbe invoked.
 3. The method according to claim 2, wherein the step offorming leaf nodes comprises at least one of action node and sub-logicnode, and further comprises: defining the interface description of theaction node and/or sub-logic; and binding the implementation modules ofthe action and the sub-logic according to said interface description. 4.The method according to claim 1, wherein said annotating step comprisesattaching at least one of the following annotations: preconditiondefining the condition to be met for performing the corresponding node;postcondition defining the condition to be met for leaving thecorresponding node; pre-task defining the task to be performed beforeperforming the corresponding node; post-task defining the task to beperformed before leaving the corresponding node; and the type ofintermediate node, stipulating whether the children of the intermediatenode should be performed sequentially or in parallel.
 5. A method forexecuting the processing logic established according to claim 1,comprising: traversing the tree according to the annotations, andperforming the leaf nodes of the tree according to the annotations, thuscompleting the execution of the task.
 6. The method according to claim5, wherein the leaf nodes of the tree comprises at least one of actionnode and sub-logic node, wherein, invoking atomic action program whenexecuting the action node, and invoking sub-logic when performing thesub-logic node.
 7. The method according to claim 5, wherein saidannotations includes at least one of the following: preconditiondefining the condition to be met for performing the corresponding node;postcondition defining the condition to be met for leaving thecorresponding node; pre-task defining the task to be performed beforeperforming the corresponding node; post-task defining the task to beperformed before leaving the corresponding node; the type ofintermediate node, stipulating whether the children of the intermediatenode should be performed sequentially or in parallel. and the methodfurther comprises: when the traversing reaches a node, checking itsannotations, and determining whether to perform the node according tosaid precondition and whether to leave the node according to saidpostcondition, executing the pre-task before executing the nodeaccording to the pre-task, executing the post-task before leaving thenode according to the post-task, and, according to the type of the node,determining whether a depth-first traversing algorithm or abroadness-first traversing algorithm should be performed with respect tothe children of the node.
 8. A processing logic modeling apparatus tomodel a task, comprising an editor comprising: a tree editor, forediting a tree corresponding to a processing logic and showing how thetask is decomposed into at least one level of sub-tasks; annotationeditor, for editing annotations for the nodes of the tree, theannotations representing the relations between the nodes of variouslevels; and interpreter, for mapping the tree and the annotations intoscript of the processing logic.
 9. The apparatus according to claim 8,wherein, said editor further comprises a graphical user interface, onwhich various graphical elements are provided or defined by the user,graphics representing the tree and the annotations are edited with saidtree editor and said annotation editor on the graphical user interfaceby using said graphical elements, and said interpreter comprises meansfor mapping a predetermined graphical element into a predeterminedscript section.
 10. The apparatus according to claim 9, wherein saidgraphical elements includes graphical elements corresponding to the treestructure and graphical elements corresponding to the annotations. 11.The apparatus according to claim 9, wherein said graphical elementsincludes formatted text.
 12. The apparatus according to claim 8, furthercomprising a debugger for simulatively performing the processing logic,either automatically or manually, either globally or locally, so as tofind out and display the potential bug in the resulted processing logic.13. A processing logic executing apparatus comprising an identifyingmeans for identifying the annotations in the processing logic scriptproduced by the processing logic modeling apparatus according to claim8, so that the executing apparatus traverses the tree according to theannotations and executes the processing logic.
 14. An article ofmanufacture comprising a computer usable medium having computer readableprogram code means embodied therein for causing modeling of a task, thecomputer readable program code means in said article of manufacturecomprising computer readable program code means for causing a computerto effect the steps of claim
 1. 15. An article of manufacture comprisinga computer usable medium having computer readable program code meansembodied therein for causing execution of the processing logic, thecomputer readable program code means in said article of manufacturecomprising computer readable program code means for causing a computerto effect the steps of claim
 5. 16. A program storage device readable bymachine, tangibly embodying a program of instructions executable by themachine to perform method steps for executing the processing logic, saidmethod steps comprising the steps of claim
 5. 17. The method accordingto claim 1, wherein: said tree structure forming step comprises: formingleaf nodes comprising at least one of action node and sub-logic node,wherein, the action node corresponds to atomic action program that couldbe invoked, and the sub-logic node corresponds to sub-logic that couldbe invoked; the step of forming leaf nodes comprises at least one ofaction node and sub-logic node, and further comprises: defining theinterface description of the action node and/or sub-logic, and bindingthe implementation modules of the action and the sub-logic according tosaid interface description; and the annotating step comprises attachingat least one of the following annotations: precondition defining thecondition to be met for performing the corresponding node; postconditiondefining the condition to be met for leaving the corresponding node;pre-task defining the task to be performed before performing thecorresponding node; post-task defining the task to be performed beforeleaving the corresponding node; and the type of intermediate node,stipulating whether the children of the intermediate node should beperformed sequentially or in parallel.
 18. The method according to claim5, wherein: the leaf nodes of the tree comprises at least one of actionnode and sub-logic node, wherein, invoking atomic action program whenexecuting the action node, and invoking sub-logic when performing thesub-logic node; said annotations includes at least one of the following:precondition defining the condition to be met for performing thecorresponding node; postcondition defining the condition to be met forleaving the corresponding node; pre-task defining the task to beperformed before performing the corresponding node; post-task definingthe task to be performed before leaving the corresponding node; the typeof intermediate node, stipulating whether the children of theintermediate node should be performed sequentially or in parallel. andthe method further comprises: when the traversing reaches a node,checking its annotations, and determining whether to perform the nodeaccording to said precondition and whether to leave the node accordingto said postcondition, executing the pre-task before executing the nodeaccording to the pre-task, executing the post-task before leaving thenode according to the post-task, and, according to the type of the node,determining whether a depth-first traversing algorithm or abroadness-first traversing algorithm should be performed with respect tothe children of the node.
 19. A computer program product comprising acomputer usable medium having computer readable program code meansembodied therein for causing modeling of a task, the computer readableprogram code means in said computer program product comprising computerreadable program code means for causing a computer to effect thefunctions of claim
 8. 20. A computer program product comprising acomputer usable medium having computer readable program code meansembodied therein for causing functions of a processing logic executingapparatus, the computer readable program code means in said computerprogram product comprising computer readable program code means forcausing a computer to effect the functions of claim 13.